The Intel® Core™ microarchitecture implements a hardware prefetcher (which has been referred to as the Data Cache Unit Prefetcher) which prefetches into the level-1 data (L1D) cache. Upon recognizing a pattern of loads within a cache line, the Data Cache Unit Prefetcher prefetches the next sequential cache line into the L1D cache. If each successive load was to a lower address than each previous address, the previous sequential cache line is prefetched.